Various electronic systems require high quality clock synthesis, clock distribution and data transmission networks. Many standards specify clock and data formats for accommodating the needs of the different systems in terms of the signal properties, as for example voltage swing, clock frequency and edge speed. Commonly used standards for clock distribution and data transmission are for example high current steering logic (HCSL), low voltage differential swing (LVDS), current switch mode logic (CML) and low voltage CMOS (LVCMOS). HCSL, CML and LVDS use differential signaling while LVCMOS uses single-ended rail-to-rail signaling. For each of the existing standards, different buffer types are employed. Several different circuit topologies, which are commonly used for implementing LVDS output buffers are, for example described in Bratov et al., “Architecture and Implementation of a Low-Power LVDS Output Buffer for High-Speed Applications,” IEEE Trans. on Circuits and Systems—I: Regular Papers, Vol. 53, No. 10, October 2006. The other standards may also use several different architectures and configurations.
In order to the reduce chip area and the pin count while increasing flexibility, it is desirable to provide electronic devices with output buffers, that accommodate more than one of the previously mentioned standards. Turning to FIG. 1, an example of a convention multi-standard buffer 100 can be seen. As shown, this buffer 100 generally comprises an LVDS buffer 102, an HCSL buffer 104, an LVCMOS buffer 106, and a CML buffer 108. Each of these buffers 102, 104, 106, and 108 receive the input signal IN and can be enabled, respectively, by enable signals SNLVDS, ENHCSL, ENLVCMOS, and ENCML. Based on these enable signals SNLVDS, ENHCSL, ENLVCMOS, and ENCML, the appropriate buffer 102, 104, 106, or 108 can be enabled or activated. A problem with this configuration, however, is that a considerable amount of area is wasted. Therefore there is a need for an improved multi-standard buffer.
Some other conventional circuits are: U.S. Pat. No. 7,598,779; U.S. Patent Pre-Grant Publ. No. 2007/0024320; and U.S. Patent Pre-Grant Publ. No. 2003/0193350.